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rev. 4106f?8051?10/02 features mpeg i/ii-layer 3 hardwired decoder ? stand-alone mp3 decoder ? 48, 44.1, 32, 24, 22.05, 16 khz sampling frequency ? separated digital volume control on left and right channels (software control using 31 steps) ? bass, medium, and treble control (31 steps) ? bass boost sound effect ? ancillary data extraction ? ?crc error? and ?mpeg frame synchronization? indicators programmable audio output for interfacing with common audio dac ? pcm format compatible ?i 2 s format compatible 8-bit mcu c51 core based (f max =20mhz) 2304 bytes of internal ram 64k bytes of code memory ? flash: at89c51snd1c, rom: at83c51snd1c 4k bytes of boot flash memory (at89c51snd1c) ? isp: download from usb or uart to any external memory cards usb rev 1.1 controller ? ?full speed? data transmission built-in pll ? mp3 audio clocks ?usbclock multimedia card? interface compatibility atmel dataflash ? spi interface compatibility ide/atapi interface 2 channels 10-bit adc, 8 khz (8-true bit) ? battery voltage monitoring ? voice recording controlled by software up to 44 bits of general-purpose i/os: ? 4-bit interrupt keyboard port for a 4 x n matrix ? smartmedia? software interface standard two 16-bit timers/counters hardware watchdog timer standard full duplex uart with baud rate generator two wire interface (twi) master and slave modes controller spi master and slave modes controller power management ? power-on reset ? software programmable mcu clock ? idle mode, power-down mode operating conditions: ?3v, 10%, 25 ma typical operating at 25c ? temperature range: -40 cto+85 c packages ? tqfp80, plcc84 (development board) ?dice description the at8xc51snd1c are fully integrated stand-alone hardwired mpeg i/ii-layer 3 decoders with a c51 microcontroller core handling data flow and mp3-player control. the at89c51snd1c includes 64k bytes of flash memory and allows in-system pro- gramming through an embedded 4k bytes of boot flash memory. single-chip microcontroller with mp3 decoder and man-machine interface at83c51snd1c at89c51snd1c preliminary summary
2 at8xc51snd1c 4106f?8051?10/02 the at83c51snd1c includes 64k bytes of rom memory. the at8xc51snd1c includes 2304 bytes of ram memory. the at8xc51snd1c provides all necessary features for man machine interface like timers, keyboard port, serial or parallel interface (usb, twi, spi, ide), adc input, i 2 s output, and all external memory interface (nand or nor flash, smartmedia, multime- dia, dataflash cards). typical applications mp3 player pda, camera, mobile phone mp3 car audio/multimedia mp3 home audio/multimedia mp3
3 at8xc51snd1c 4106f?8051?10/02 pin descriptions figure 1. at8xc51snd1c, 80-pin tqfp package at89c51snd1c-ro (flash) at83c51snd1c-ro (rom) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss v dd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.1/txd p3.2/ int0 p3.3/ int1 p3.4/t0 p3.0/rxd 1 2 3 4 5 6 7 8 13 11 10 p2.2/a10 p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p0.0/ad0 pvss vss x2 x1 tst vss 9 12 14 15 16 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss v dd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss a v dd p3.7/rd p3.6/wr p3.5/t1 v dd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt p v dd v dd p1.6/scl 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80 ale isp u v dd uvss p5.0 p5.1 p4.7 p4.6 d- d+ p5.3 p5.2 vss v dd p4.5 p4.4
4 at8xc51snd1c 4106f?8051?10/02 figure 2. at8xc51snd1c 84-pin plcc package (1) note: 1. only samples for development board. pin descriptions all at8xc51snd1c signals are detailed by functionality in table 1 through table 14. at89c51snd1c-sr (flash) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss v dd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.2/int0 65 64 63 62 61 60 59 58 55 56 57 12 13 14 15 16 17 22 20 19 33 34 35 36 37 4 3 2 1 84 83 82 81 80 79 78 nc p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p5.0 pavss vss x2 nc x1 p3.1/txd 18 21 23 24 25 38 39 40 41 42 69 68 67 66 70 5 6 7 8 9 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss v dd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss a v dd vss v dd p3.7/rd p3.0/rxd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pa v dd v dd p1.6/scl 26 43 tst p5.2 p0.0/ad0 77 p2.2/a10 54 ale isp nc p5.1 p4.7 p4.6 76 75 10 11 28 27 29 30 31 32 u v dd uvss 44 45 46 47 48 49 50 51 52 53 74 73 72 71 p4.4 p4.5 v dd vss d- d+ nc p5.3 table 1. ports signal description signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bi-directional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.7:0 i/o port 1 p1 is an 8-bit bi-directional i/o port with internal pull-ups. kin3:0 scl sda
5 at8xc51snd1c 4106f?8051?10/02 p2.7:0 i/o port 2 p2 is an 8-bit bi-directional i/o port with internal pull-ups. a15:8 p3.7:0 i/o port 3 p3 is an 8-bit bi-directional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.7:0 i/o port 4 p4 is an 8-bit bi-directional i/o port with internal pull-ups. miso mosi sck ss p5.3:0 i/o port 5 p5 is a 4-bit bi-directional i/o port with internal pull-ups. - table 2. clock signal description signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. - table 3. timer 0 and timer 1 signal description signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bitie0issetbyafallingedgeonint0 .ifbitit0iscleared,bitie0isset by a low level on int0 . p3.2 int1 i timer 1 gate input int1 serves as external run control for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bitie1issetbyafallingedgeonint1 .ifbitit1iscleared,bitie1isset by a low level on int1 . p3.3 table 1. ports signal description (continued) signal name type description alternate function
6 at8xc51snd1c 4106f?8051?10/02 t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 table 4. audio interface signal description signal name type description alternate function dclk o dac data bit clock - dout o dac audio data - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchronized to the digital audio data (dout) and the channel selection signal (dsel). - table 5. usb controller signal description signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k ? pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port - table 6. mutimediacard interface signal description signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bi-directional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bi-directional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - table 3. timer 0 and timer 1 signal description (continued) signal name type description alternate function
7 at8xc51snd1c 4106f?8051?10/02 table 7. uart signal description signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 table 8. spi controller signal description signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p4.0 mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p4.1 sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p4.2 ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p4.3 table 9. twi controller signal description signal name type description alternate function scl i/o twiserialclock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sda i/o twiserialdata sda is the bi-directional twi data line. p1.7 table 10. a/d converter signal description signal name type description alternate function ain1:0 i a/d converter analog inputs - arefp i analog positive voltage reference input - arefn i analog negative voltage reference input this pin is internally connected to avss. -
8 at8xc51snd1c 4106f?8051?10/02 table 11. keypad interface signal description signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 table 12. external access signal description signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the external memory or the ide interface. p0.7:0 ale o address latch enable output ale signals the start of an external bus cycle and indicates that valid address information is available on lines a7:0. an external latch is used to demultiplex the address from address/data bus. - isp i/o isp enable input this signal must be held to gnd through a pull-down resistor at the falling reset to force execution of the internal bootloader. - rd o read signal read signal asserted during external data memory read operation. p3.7 wr o write signal write signal asserted during external data memory write operation. p3.6 table 13. system signal description signal name type description alternate function rst i reset input holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and v dd . assertingrstwhenthechipisinidlemodeorpower-downmode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . -
9 at8xc51snd1c 4106f?8051?10/02 table 14. power signal description signal name type description alternate function v dd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - a v dd pwr analog supply voltage connect this pin to +3v supply voltage. - avss gnd analog ground connect this pin to ground. - p v dd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - u v dd pwr usb supply voltage connect this pin to +3v supply voltage. - uvss gnd usb ground connect this pin to ground. -
10 at8xc51snd1c 4106f?8051?10/02 internal pin structure notes: 1. for information on resistors value, input/output levels, and drive capability, refer to the section ?dc characteristics?, page 24. 2. when the twi controller is enabled, p 1 ,p 2 ,andp 3 transistors are disabled allowing pseudo open-drain structure. 3. in port 2, p 1 transistor is continuously driven when outputting a high level bit address (a15:8). table 15. detailed internal pin structure circuit (1) type pins input tst input/output rst input/output p1 (2) p2 (3) p3 p4 p53:0 input/output p0 mcmd mdat isp output ale sclk dclk dout dsel mclk input/output d+ d- r tst v dd r rst vss p v dd watchdog output p 3 vss n p 1 v dd v dd 2osc latch output periods p 2 v dd vss n p v dd vss n p v dd d+ d-
11 at8xc51snd1c 4106f?8051?10/02 block diagram figure 3. at8xc51snd1c block diagram 8-bit internal bus clock and pll unit c51 (x2 core) ram 2304 bytes flash rom interrupt handler unit filt x2 x1 mp3 decoder unit twi controller mmc interface i/o scl sda mdat p0-p5 10-bit a-to-d converter vss v dd keyboard interface kin3:0 i 2 s/pcm audio interface avss a v dd note: 1 alternate function of port 1 ain1:0 ports int0 int1 mosi miso 3 alternate function of port 3 4 alternate function of port 4 timers 0/1 t1 t0 spi/dataflash controller mclk mcmd sck rst aref dsel dclk sclk dout 64k bytes usb controller d+ d- uart rxd txd ide interface ss watchdog flash boot 4k bytes isp uvss u v dd and brg ale 3 3 33 3 3444411 1 or 10-bit adc
12 at8xc51snd1c 4106f?8051?10/02 application information figure 4. at8xc51snd1c typical application with on-board atmel dataflash and twi lcd figure 5. at8xc51snd1c typical application with on-board atmel dataflash and lcd ref. battery dout dclk dsel sclk p1.4 p1.5 ain0 mclk x1 x2 vss avss vrefp vrefn v dd a v dd ain1 mdat mcmd mmc1 mmc2 audio dac rst lcd p1.7/sda p1.6/scl p1.1/kin1 p0.0 p0.1 p1.2/kin2 p1.3/kin3 p0.2 p0.3 p1.0/kin0 filt pvss dataflash p4.2/sck p4.0/si p4.1/so memories p4n at8xc51snd1c usb port d+ d- u v dd uvss ref. battery dataflash dout dclk dsel sclk p1.4 p1.5 ain0 mclk x1 x2 vss avss vrefp vrefn v dd a v dd ain1 mdat mcmd p4.2/sck p4.0/si p4.1/so mmc1 mmc2 audio dac rst p1.3 p1.0/kin0 p0.0 p0.1 p1.1/kin1 p1.2/kin2 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 lcd p1.7/sda p1.6/scl filt pvss memories p4.n at8xc51snd1c usb port d+ d- u v dd uvss
13 at8xc51snd1c 4106f?8051?10/02 figure 6. at8xc51snd1c typical application with on-board ssfdc flash figure 7. at8xc51snd1c typical application with ide cd-rom drive ref. battery usb port smartmedia ssfdc memories or smartmedia cards dout dclk dsel sclk p3.4 p3.5 ain0 d+ mclk x1 x2 vss avss vrefp vrefn v dd a v dd ain1 mdat mcmd p3.6/ wr p3.7/ rd mmc1 mmc2 audio dac rst d- p1.1/kin1 p0.0 p0.1 p1.2/kin2 p1.3/kin3 p0.2 p0.3 p1.0/kin0 filt pvss at8xc51snd1c p2 p0 p4.2 p4.4 p4.5 p4.6 p4.7 lcd p4.0 p4.1 u v dd uvss ref. battery ide cd-rom dout dclk dsel sclk p3.4 p3.5 ain0 mclk x1 x2 vss avss vrefp vrefn v dd a v dd ain1 mdat mcmd mmc1 mmc2 audio dac rst p4.2 p1.0/kin0 p0.0 p0.1 p1.1/kin1 p1.2/kin2 p0.2 p0.3 p4.4 p4.5 p4.6 p4.7 lcd p1.7/sda p1.6/scl filt pvss at8xc51snd1c p3.6/ wr p3.7/ rd p2 p0 p4.0 p4.1 usb port d+ d- u v dd uvss
14 at8xc51snd1c 4106f?8051?10/02 address spaces the at8xc51snd1c derivatives implement four different address spaces: program/code memory boot memory data memory special function registers (sfrs) code memory the at89c51snd1c and at83c51snd1c implement 64k bytes of on-chip pro- gram/code memory. the at83c51snd1c product provides the internal program/code memory in rom technology while the at89c51snd1c product provides it in flash technology. the flash memory increases rom functionality by enabling in-circuit electrical erasure and programming. thanks to the internal charge pump, the high voltage needed for pro- gramming or erasing flash cells is generated on-chip using the standard v dd voltage. thus, the at89c51snd1c can be programmed using only one voltage and allows in application software programming commonly known as iap. hardware programming mode is also available using specific programming tools. boot memory the at89c51snd1c implements 4k bytes of on-chip boot memory provided in flash technology. this boot memory is delivered programmed with a standard bootloader soft- ware allowing in-system programming commonly known as isp. it also contains some application programming interfaces routines commonly known as api allowing user to develop his own bootloader. data memory the at8xc51snd1 derivatives implement 2304 bytes of on-chip data ram. this mem- ory is divided in two separate areas: 256 bytes of on-chip ram memory (standard c51 memory). 2048 bytes of on-chip expanded ram memory (eram accessible via movx instructions).
15 at8xc51snd1c 4106f?8051?10/02 special function registers the special function registers (sfrs) of the at8xc51snd1 derivatives fall into the categories detailed in table 16 through table 32. the relative addresses of these sfrs are provided together with their reset values in table 33. in this table, the bit-address- able registers are identified by note 1. table 16. c51coresfrs mnemonicaddname 76 5 432 10 acc e0h accumulator ? ? ? ? ? ? ? ? b f0hbregister ???????? psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer ? ? ? ? ? ? ? ? dpl 82h data pointer low byte ???????? dph 83h data pointer high byte ???????? table 17. system management sfrs mnemonicaddname 76 5 432 10 pcon 87h power control smod1 smod0 ? ? gf1 gf0 pd idl auxr 8eh auxiliary register 0 ? ext16 m0 dphdis xrs1 xrs0 extram ao auxr1 a2h auxiliary register 1 ? ? enboot ? gf3 0 ? dps nvers fbh version number nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 table 18. pll and system clock sfrs mnemonicaddname 76 5 432 10 ckcon 8fh clock control ? ? ? ? ? ? ? x2 pllcon e9h pll control r1 r0 ? ? pllres ? pllen plock pllndiv eeh pll n divider ? n6 n5 n4 n3 n2 n1 n0 pllrdivefhpllrdivider r9r8r7r6r5r4r3r2
16 at8xc51snd1c 4106f?8051?10/02 table 19. interrupt sfrs mnemonicaddname 76 5 432 10 ien0 a8h interrupt enable control 0 ea eaud emp3 es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 ? eusb ? ekb eadc espi ei2c emmc iph0 b7h interrupt priority control high 0 ? iphaud iphmp3 iphs ipht1 iphx1 ipht0 iphx0 ipl0 b8h interrupt priority control low 0 ? iplaud iplmp3 ipls iplt1 iplx1 iplt0 iplx0 iph1 b3h interrupt priority control high 1 ? iphusb ? iphkb iphadc iphspi iphi2c iphmmc ipl1 b2h interrupt priority control low 1 ? iplusb ? iplkb ipladc iplspi ipli2c iplmmc table 20. port sfrs mnemonicaddname 76 5 432 10 p0 80h 8-bit port 0 ? ? ? ? ? ? ? ? p1 90h 8-bit port 1 ? ? ? ? ? ? ? ? p2 a0h 8-bit port 2 ? ? ? ? ? ? ? ? p3 b0h 8-bit port 3 ? ? ? ? ? ? ? ? p4 c0h 8-bit port 4 ? ? ? ? ? ? ? ? p5 d8h 4-bit port 5 ? ? ? ? ? ? ? ? table 21. flash memory sfr mnemonicaddname 76 5 432 10 fcon d1h flash control fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy table 22. timer sfrs mnemonicaddname 76 5 432 10 tcon 88h timer/counter 0 and 1control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 tl0 8ah timer/counter 0 low byte ???????? th0 8ch timer/counter 0 high byte ???????? tl1 8bh timer/counter 1 low byte ????????
17 at8xc51snd1c 4106f?8051?10/02 th1 8dh timer/counter 1 high byte ???????? wdtrst a6h watchdog timer reset ???????? wdtprg a7h watchdog timer program ? ? ? ? ? wto2 wto1 wto0 table 22. timer sfrs (continued) mnemonicaddname 76 5 432 10 table 23. mp3 decoder sfrs mnemonicaddname 76 5 432 10 mp3con aah mp3 control mpen mpbbst crcen mskanc mskreq msklay msksyn mskcrc mp3sta c8h mp3 status mpanc mpreq errlay errsyn errcrc mpfs1 mpfs0 mpver mp3sta1 afh mp3 status 1 ? ? ? mpfreq mpbreq ? ? ? mp3dat ach mp3 data mpd7 mpd6 mpd5 mpd4 mpd3 mpd2 mpd1 mpd0 mp3anc adh mp3 ancillary data and7 and6 and5 and4 and3 and2 and1 and0 mp3vol 9eh mp3 audio volume control left ? ? ? vol4 vol3 vol2 vol1 vol0 mp3vor 9fh mp3 audio volume control right ? ? ? vor4 vor3 vor2 vor1 vor0 mp3bas b4h mp3 audio bass control ? ? ? bas4 bas3 bas2 bas1 bas0 mp3med b5h mp3 audio medium control ? ? ? med4 med3 med2 med1 med0 mp3tre b6h mp3 audio treble control ? ? ? tre4 tre3 tre2 tre1 tre0 mp3clk ebh mp3 clock divider ? ? ? mpcd4 mpcd3 mpcd2 mpcd1 mpcd0 table 24. audio interface sfrs mnemonicaddname 76 5 432 10 audcon0 9ah audio control 0 just4 just3 just2 just1 just0 pol dsiz hlr audcon1 9bh audio control 1 src drqen msreq mudrn ? dup1 dup0 auden audsta 9ch audio status sreq udrn aubusy ? ? ? ? ? auddat 9dh audio data aud7 aud6 aud5 aud4 aud3 aud2 aud1 aud0 audclk ech audio clock divider ? ? ? aucd4 aucd3 aucd2 aucd1 aucd0
18 at8xc51snd1c 4106f?8051?10/02 table 25. usb controller sfrs mnemonicaddname 76 5 432 10 usbcon bch usb global control usbe suspclk sdrmwup ? uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 usbint bdh usb global interrupt ? ? wupcpu eorint sofint ? ? spint usbien beh usb global interrupt enable ? ? ewupcpu eeorint esofint ? ? espint uepnum c7h usb endpoint number ? ? ? ? ? ? epnum1 epnum0 uepconx d4h usb endpoint x control epen ? ? ? dtgl epdir eptype1 eptype0 uepstax ceh usb endpoint x status dir ? stallrq txrdy stlcrc rxsetup rxout txcmp ueprst d5h usb endpoint reset ? ? ? ? ep3rst ep2rst ep1rst ep0rst uepint f8h usb endpoint interrupt ? ? ? ? ep3int ep2int ep1int ep0int uepien c2h usb endpoint interrupt enable ? ? ? ? ep3inte ep2inte ep1inte ep0inte uepdatx cfh usb endpoint x fifo data fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 ubyctx e2h usb endpoint x byte counter - byct6 byct5 byct4 byct3 byct2 byct1 byct0 ufnuml bah usb frame number low fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 ufnumh bbh usb frame number high ? ? crcok crcerr ? fnum10 fnum9 fnum8 usbclk eah usb clock divider ? ? ? ? ? ? usbcd1 usbcd0 table 26. mmc controller sfrs mnemonicaddname 76 5 432 10 mmcon0 e4h mmc control 0 drptr dtptr crptr ctptr mblock dfmt rfmt crcdis mmcon1 e5h mmc control 1 blen3 blen2 blen1 blen0 datdir daten respen cmden mmcon2 e6h mmc control 2 mmcen dcr ccr ? ? datd1 datd0 flowc mmsta deh mmc control and status ? ? cbusy crc16s datfs crc7s respfs cflck mmint e7h mmc interrupt mcbi eori eoci eofi f2fi f1fi f2ei f1ei mmmsk dfh mmc interrupt mask mcbm eorm eocm eofm f2fm f1fm f2em f1em mmcmd ddh mmc command mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 mmdat dch mmc data md7 md6 md5 md4 md3 md2 md1 md0 mmclk edh mmc clock divider mmcd7 mmcd6 mmcd5 mmcd4 mmcd3 mmcd2 mmcd1 mmcd0
19 at8xc51snd1c 4106f?8051?10/02 table 27. ide interface sfr mnemonicaddname 76 5 432 10 dat16h f9h high order data byte d15 d14 d13 d12 d11 d10 d9 d8 table 28. serial i/o port sfrs mnemonicaddname 7 6 5 432 10 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer ? ? ? ? ? ? ? ? saden b9h slave address mask ? ? ? ? ? ? ? ? saddr a9h slave address ? ? ? ? ? ? ? ? bdrcon 92h baud rate control ? ? ? brr tbck rbck spd src brl 91h baud rate reload ? ? ? ? ? ? ? ? table 29. spi controller sfrs mnemonicaddname 76 5 432 10 spcon c3h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta c4h spi status spif wcol ? modf ? ? ? ? spdat c5h spi data spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 table 30. twi controller sfrs mnemonicaddname 76 5 432 10 sscon 93h synchronous serial control sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 sssta 94h synchronous serial status ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 ssdat 95h synchronous serial data ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 ssadr 96h synchronous serial address ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc table 31. keyboard interface sfrs mnemonicaddname 76 5 432 10 kbcon a3h keyboard control kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 kbsta a4h keyboard status kpde ? ? ? kinf3 kinf2 kinf1 kinf0
20 at8xc51snd1c 4106f?8051?10/02 table 32. a/d controller sfrs mnemonicaddname 76 5 432 10 adcon f3h adc control ? adidl aden adeoc adsst ? ? adcs adclk f2h adc clock divider ? ? ? adcd4 adcd3 adcd2 adcd1 adcd0 addl f4h adc data low byte ? ? ? ? ? ? adat1 adat0 addh f5h adc data high byte adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2
21 at8xc51snd1c 4106f?8051?10/02 notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. nvers reset value depends on the silicon version. 3. fcon register is only available in at89c51snd1c product. 4. fcon reset value is 00h in case of reset with hardware condition. 5. ckcon reset value depends on the x2b bit (programmed or unprogrammed) in the hardware byte. table 33. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 dat16h xxxx xxxx nvers 2 1000 0100 ffh f0h b 1 0000 0000 adclk 0000 0000 adcon 0000 0000 addl 0000 0000 addh 0000 0000 f7h e8h pllcon 0000 1000 usbclk 0000 0000 mp3clk 0000 0000 audclk 0000 0000 mmclk 0000 0000 pllndiv 0000 0000 pllrdiv 0000 0000 efh e0h acc 1 0000 0000 ubyctlx 0000 0000 mmcon0 0000 0000 mmcon1 0000 0000 mmcon2 0000 0000 mmint 0000 0011 e7h d8h p5 1 x xxx 1111 mmdat 1111 1111 mmcmd 1111 1111 mmsta 0000 0000 mmmsk 1111 1111 dfh d0h psw 1 0000 0000 fcon 3 1111 0000 4 uepconx 0000 0000 ueprst 0000 0000 d7h c8h mp3sta 1 0000 0001 uepstax 0000 0000 uepdatx 0000 0000 cfh c0h p4 1 1111 1111 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat xxxx xxxx usbaddr 1000 0000 uepnum 0000 0000 c7h b8h ipl0 1 x000 0000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0001 0000 bfh b0h p3 1 1111 1111 ien1 0000 0000 ipl1 0000 0000 iph1 0000 0000 mp3bas 0000 0000 mp3med 0000 0000 mp3tre 0000 0000 iph0 x000 0000 b7h a8h ien0 1 0000 0000 saddr 0000 0000 mp3con 0011 1111 mp3dat 0000 0000 mp3anc 0000 0000 mp3sta1 0100 0001 afh a0h p2 1 1111 1111 auxr1 xxxx 00x0 kbcon 0000 1111 kbsta 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx audcon0 0000 1000 audcon1 1011 0010 audsta 1100 0000 auddat 1111 1111 mp3vol 0000 0000 mp3vor 0000 0000 9fh 90h p1 1 1111 1111 brl 0000 0000 bdrcon xxx0 0000 sscon 0000 0000 sssta 1111 1000 ssdat 1111 1111 ssadr 1111 1110 97h 88h tcon 1 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr x000 1101 ckcon 0000 000x 5 8fh 80h p0 1 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon xxxx 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
22 at8xc51snd1c 4106f?8051?10/02 peripherals clock generator system the at8xc51snd1c internal clocks are extracted from an on-chip pll fed by an on- chip oscillator. four clocks are generated respectively for the c51 core, the mp3 decoder, the audio interface, and the other peripherals. the c51 and peripheral clocks are derived from the oscillator clock. the mp3 decoder clock is generated by dividing the pll output clock. the audio interface sample rates are also obtained by dividing the pll output clock. ports the at8xc51snd1c implement five 8-bit ports (p0 - p4) and one 4-bit port (p5). in addition to performing general-purpose i/os, some ports are capable of external data memory operations; others allow for alternate functions. all i/o ports are bi-directional. each port contains a latch, an output driver and an input buffer. port 0 and port 2 output drivers and input buffers facilitate external memory operations. some port 1, port 3 and port 4 pins serve for both general-purpose i/os and alternate functions. timers/counters the at8xc51snd1c implement the two general-purpose, 16-bit timers/counters of a standard c51. they are identified as timer 0, timer 1, and can independently be config- ured each to operate in a variety of modes as a timer or as an event counter. when operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer/counter counts neg- ative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. watchdog timer the at8xc51snd1c implement a hardware watchdog timer that automatically resets the chip if it is allowed to time out. the wdt provides a means of recovering from rou- tines that do not complete successfully due to software or hardware malfunctions. mp3 decoder the at8xc51snd1c implements a mpeg i/ii audio layer 3 decoder (mp3 decoder). in mpeg i (iso 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 khz. among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining cd audio quality. for example, 3 minutes of cd audio (16-bit pcm, 44.1 khz) data, which needs about 32m bytes of storage, can be encoded into only 2.7 mbytes of mpeg i audio layer 3 data. in mpeg ii (iso 13818-3), three additional sampling frequencies: 24, 22.05, and 16 khz are supported for low bit rates applications. the at8xc51snd1c can decode in real-time the mpeg i audio layer 3 encoded data into a pcm audio data, and also supports mpeg ii audio layer 3 additional frequencies. additional features are supported by the at8xc51snd1c mp3 decoder such as vol- ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction. audio output interface the at8xc51snd1c implements an audio output interface allowing the decoded audio bitstream to be output in various formats. it is compatible with right and left justification pcm and i 2 s formats and the on-chip pll (see section ?clock generator system?) allows connection of almost all of the commercial audio dac families available on the market.
23 at8xc51snd1c 4106f?8051?10/02 universal serial bus interface the at8xc51snd1c implement a full-speed usb interface. it can be used for the fol- lowing purposes: download of mp3 encoded audio files by supporting the usb mass storage class. in-system programming by supporting the usb firmware upgrade class. multimedia card interface the at8xc51snd1c implement a multimedia card (mmc) interface compliant to the v2.2 specification in multimedia card mode. the mmc allows storage of mp3 encoded audio files in removable flash memory cards that can be easily plugged to, or removed from the application. it can also be used for in-system programming. ide/atapi interface the at8xc51snd1c provide an ide/atapi interface allowing connection of devices such as cd-rom reader, compactflash ? cards, hard disk drive, etc. it consists of a 16-bit bi-directional bus part of the low-level ansi ata/atapi specification. it is pro- vided for mass storage interfaces but could be used for in-system programming using cd-rom. serial i/o interface the at8xc51snd1c implement a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex universal asynchro- nous receiver transmitter (uart) communication modes. it is provided for the following purposes: in-system programming. remote control of the at8xc51snd1c by a host. serial peripheral interface the at8xc51snd1c implement a serial peripheral interface (spi) supporting master and slave modes. it is provided for the following purposes: interfacing dataflash memory and dataflash cards for mp3 encoded audio files storage remote control of the at8xc51snd1c by a host in-system programming twi controller the at8xc51snd1c implements a twi controller supporting the four standard master and slave modes with multimaster capability. it is provided for the following purposes: connection of slave devices like lcd controller, audio dac? remote control of the at8xc51snd1c by a host in-system programming a/d controller the at8xc51snd1c implements a 2-channel 10-bit (8 true bits) analog-to-digital con- verter (adc). it is provided for the following purposes: battery monitoring voice recording corded remote control keyboard interface the at8xc51snd1c implement a keyboard interface allowing connection of 4 x n matrix keyboard. it is based on 4 inputs with programmable interrupt capability on both high or low level. these inputs are available as an alternate function of p1.3:0 and allow exit from idle and power-down modes.
24 at8xc51snd1c 4106f?8051?10/02 electrical characteristics absolute maximum rating dc characteristics digital logic storage temperature ......................................... -65 to +150 c voltage on any other pin to v ss ...................................... -0.3 to +4.0v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w ambient temperature under bias........................ -40 to +85 c v dd ........................................................................................... 2.7 to 3.3v note: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 34. digital dc characteristics v dd = 2.7 to 3.3v , t a =-40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2 v dd -0.1 v v ih1 input high voltage (except rst) 0.2 v dd +0.9 v dd v v ih2 input high voltage (rst) 0.7 v dd v dd +0.5 v v ol1 output low voltage (except p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol =1.6ma v ol2 output low voltage (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol =3.2ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd -0.7 v i oh =-30 a v oh2 output high voltage (p0, p2 address mode, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd -0.7 v i oh =-3.2ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 av in =0.45v
25 at8xc51snd1c 4106f?8051?10/02 note: 1. typical values are obtained using v dd =3vand t a =25 c. they are not tested and there is no guarantee on these values. figure 8. i dd /i dl versus x tal frequency; v dd = 2.7 to 3.3v i li input leakage current (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a0.45 26 at8xc51snd1c 4106f?8051?10/02 i dd, i dl and i pd test conditions figure 9. i dd test condition, active mode figure 10. i dl test condition, idle mode figure 11. i pd test condition, power-down mode x2 v dd clock signal rst vss tst x1 p0 (nc) idd all other pins are unconnected v dd vss v dd v dd x2 v dd clock signal rst vss tst x1 p0 (nc) idl all other pins are unconnected vss v dd vss v dd x2 v dd rst vss mcmd x1 p0 (nc) ipd all other pins are unconnected vss v dd vss v dd tst mdat
27 at8xc51snd1c 4106f?8051?10/02 a-to-d converter oscillator and crystal schematic figure 12. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in spe- cial cases (max 10 pf). x1 and x2 may not be used to drive other circuits. parameters table 36. oscillator and crystal characteristics v dd = 2.7 to 3.3v , t a =-40 to +85 c table 35. a-to-d converter dc characteristics v dd = 2.7 to 3.3v , t a =-40 to +85 c symbol parameter min typ max units test conditions a v dd analog supply voltage 2.7 3.3 v ai dd analog operating supply current 600 a a v dd =3.3v ain1:0 = 0 to a v dd ai pd analog standby current 2 a a v dd =3.3v aden = 0 or pd = 1 av in analog input voltage av ss a v dd v av ref reference voltage a refn a refp av ss 2.4 a v dd v v r ref aref input resistance 10 30 k ? t a =25 c c ia analog input capacitance 10 pf t a =25 c v ss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - vss) 10 pf c x2 internal capacitance (x2 - vss) 10 pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 ? cs crystal shunt capacitance 6 pf
28 at8xc51snd1c 4106f?8051?10/02 phase lock loop schematic figure 13. pll filter connection parameters table 37. pll filter characteristics v dd =2.7to3.3v,t a =-40 to +85 c in-system programming schematic figure 14. isp pull-down connection parameters table 38. isp pull-down characteristics v dd = 2.7 to 3.3v , t a =-40 to +85 c vss pfilt r c1 c2 vss symbol parameter min typ max unit r filter resistor 100 ? c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf v ss isp risp symbol parameter min typ max unit r isp isp pull-down resistor 2.2 k ?
29 at8xc51snd1c 4106f?8051?10/02 ac characteristics external 8-bit bus cycles definition of symbols table 39. external 8-bit bus cycles timing symbol definitions timings test conditions: capacitive load on all pins = 50 pf. table 40. external 8-bit bus cycle ? data read ac timings v dd =2.7to3.3v,t a =-40 to +85 c signals conditions aaddress hhigh ddatain llow l ale v valid q data out x no longer valid rrd zfloating wwr symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2 t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5 t clcl -20 ns t llax address hold after ale low t clcl -20 0.5 t clcl -20 ns t llrl ale low to rd low 3 t clcl -30 1.5 t clcl -30 ns t rlrh rd pulse width 6 t clcl -25 3 t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5 t clcl -20 0.5 t clcl +20 ns t avdv address valid to valid data in 9 t clcl -65 4.5 t clcl -65 ns t avrl address valid to rd low 4 t clcl -30 2 t clcl -30 ns t rldv rd low to valid data 5 t clcl -30 2.5 t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2 t clcl -25 t clcl -25 ns
30 at8xc51snd1c 4106f?8051?10/02 table 41. external 8-bit bus cycle ? data write ac timings v dd =2.7to3.3v,t a =-40 to +85 c waveforms figure 15. external 8-bit bus cycle ? data read waveforms symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns t avdv t llax t rhdx t rhdz t avll t av r l p2 p0 rd ale t lhll t rlrh data in a15:8 t rlaz t llrl t rhlh t rldv d7:0 a7:0
31 at8xc51snd1c 4106f?8051?10/02 figure 16. external 8-bit bus cycle ? data write waveforms external ide 16-bit bus cycles definition of symbols table 42. external ide 16-bit bus cycles timing symbol definitions timings test conditions: capacitive load on all pins = 50 pf. t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh a15:8 t avll t qvwh d7:0 data out t llwl a7:0 signals conditions aaddress hhigh ddatain llow l ale v valid q data out x no longer valid rrd zfloating wwr
32 at8xc51snd1c 4106f?8051?10/02 table 43. external ide 16-bit bus cycle ? data read ac timings v dd = 2.7 to 3.3v, t a =-40 to +85 c table 44. external ide 16-bit bus cycle ? data write ac timings v dd =2.7to3.3v,t a =-40 to +85 c symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t av d v address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh datavalidtowr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns
33 at8xc51snd1c 4106f?8051?10/02 waveforms figure 17. external ide 16-bit bus cycle ? data read waveforms note: d15:8 is written in dat16h sfr. figure 18. external ide 16-bit bus cycle ? data write waveforms note: d15:8 is the content of dat16h sfr. spi interface definition of symbols table 45. spi interface timing symbol definitions t av d v t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in t rlaz t llrl t rhlh t rldv d7:0 a7:0 data in d15:81 a15:8 t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh t avll t qvwh d7:0 data out t llwl a7:0 d15:81 data out a15:8 signals conditions cclock hhigh idatain llow o data out v valid x no longer valid zfloating
34 at8xc51snd1c 4106f?8051?10/02 timings table 46. spi interface master ac timing (2) v dd =2.7to3.3v,t a =-40 to +85 c notes: 1. value of this parameter depends on software. 2. test conditions: capacitive load on all pins = 100 pf symbol parameter min max unit slave mode t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch ,t slcl ss low to clock edge 200 ns t ivcl ,t ivch input data valid to clock edge 100 ns t clix ,t chix input data hold after clock edge 100 ns t clov, t chov output data valid after clock edge 100 ns t clox ,t chox output data hold time after clock edge 0 ns t clsh ,t chsh ss high after clock edge 0 ns t ivcl ,t ivch input data valid to clock edge 100 ns t clix ,t chix input data hold after clock edge 100 ns t slov ss low to output data valid 130 ns t shox output data hold after ss high 130 ns t shsl ss high to ss low note (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl ,t ivch input data valid to clock edge 50 ns t clix ,t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 65 ns t clox ,t chox output data hold time after clock edge 0 ns t ilih inputdatarisetime 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
35 at8xc51snd1c 4106f?8051?10/02 waveforms figure 19. spi slave waveforms (sscpha = 0) note: 1. not defined but generally the msb of the character, which has just been received. figure 20. spi slave waveforms (sscpha = 1) note: 1. not defined but generally the lsb of the character, which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol = 0) (input) ss (1) (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh si (input) sck (sscpol = 0) (output) ss 1 (1) (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
36 at8xc51snd1c 4106f?8051?10/02 figure 21. spi master waveforms (sscpha = 0) note: ss handled by software using general purpose port pin. figure 22. spi master waveforms (sscpha = 1) note: ss handled by software using general purpose port pin. t chcl t clch mosi (input) sck (sscpol = 0) (input) ss 1 (1) (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh t slcl t slch si (input) sck (sscpol = 0) (output) ss 1 (1) (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
37 at8xc51snd1c 4106f?8051?10/02 two-wire interface timings table 47. twi interface ac timing zv dd = 2.7 to 3.3v, t a =-40 to +85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on bus-lines sda and scl = 400 pf. 4. t clcl =t osc = one oscillator clock period. waveforms figure 23. twi waveforms symbol parameter input min max output min max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high sclhightime 14t clcl (4) 4.0 s (1) t rc sclrisetime 1 snote (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) -t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) -t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s- (2) t fd sda fall time 0.3 s0.3 s (3) t su ;dat1 t su ; sta ts u ; d at 2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t hd dat t su; dat3 start or repeated start condition start condition stop condition repeated start condition
38 at8xc51snd1c 4106f?8051?10/02 mmc interface definition of symbols table 48. mmc interface timing symbol definitions timings table 49. mmc interface ac timings v dd =2.7to3.3v,t a =0to70 c, cl 100 pf (10 cards) waveforms figure 24. mmc input-output waveforms signals conditions cclock hhigh ddatain llow o data out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox
39 at8xc51snd1c 4106f?8051?10/02 audio interface definition of symbols table 50. audio interface timing symbol definitions timings table 51. audio interface ac timings v dd =2.7to3.3v,t a =0to70 c, cl 30pf note: 32-bit format with fs = 48 khz. waveforms figure 25. audio interface waveforms signals conditions cclock hhigh o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns dclk t chch t clcx t chcx t clch t chcl dsel ddat right left t clsv t clov
40 at8xc51snd1c 4106f?8051?10/02 analog to digital converter definition of symbols table 52. analog to digital converter timing symbol definitions characteristics table 53. analog-to-digital converter ac characteristics v dd =2.7to3.3v,t a =0to70 c notes: 1. a v dd =av refp =3.0v,av ss =av refn = 0 v. adc is monotonic with no missing code. 2. the differential non-linearity is the difference between the actual step width and the ideal step width (see figure 27). 3. the integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see figure 27). 4. the offset error is the absolute difference between the straight line, which fits the actual transfer curve (after removing of gain error); and the straight line, which fits the ideal transfer curve (see figure 27). 5. the gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error); and the straight line, which fits the ideal transfer curve (see figure 27). waveforms figure 26. analog-to-digital converter internal waveforms signals conditions cclock hhigh e enable (aden bit) l low s start conversion (adsst bit) symbol parameter min max unit t clcl clock period 1.43 s t ehsh start-up time 4 s t shsl conversion time 11t clcl s d le differential non- linearity error (1)( 2) tbd lsb i le integral non- linearity error (1)(3) tbd lsb o se offset error (1)(4) tbd lsb g e gain error (1)(5) tbd % aden bit adsst bit t ehsh t shsl clk t clcl
41 at8xc51snd1c 4106f?8051?10/02 figure 27. analog to digital converter characteristics flash memory definition of symbols table 54. flash memory timing symbol definitions timings table 55. flash memory ac timing v dd =2.7to3.3v,t a =-40 to +85 c 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 offset error code out avin (lsbideal) offset error o se gain error g e ideal transfer curve 1lsb (ideal) integral non-linearity differential non-linearity center of a step example of an actual transfer curve 0 0 signals conditions sisp llow rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input isp validtorstedge 50 ns t rlsx input isp hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms
42 at8xc51snd1c 4106f?8051?10/02 waveforms figure 28. flash memory ? isp waveforms note: isp must be driven through a pull-down resistor (see section ?in-system programming?, page 28). figure 29. flash memory ? internal busy waveforms external clock drive and logic level references definition of symbols table 56. external clock timing symbol definitions timings table 57. external clock ac timings v dd =2.7to3.3v,t a =0to70 c waveforms figure 30. external clock waveform rst t svrl isp 1 t rlsx fbusy bit t bhbl signals conditions cclock hhigh llow x no longer valid symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclicratioinx2mode 40 60 % 0.45 v t clcl v dd -0.5 v ih1 v il t chcx t clch t chcl t clcx
43 at8xc51snd1c 4106f?8051?10/02 figure 31. ac testing input/output waveforms notes: 1. during ac testing, all inputs are driven at v dd -0.5v for a logic 1 and 0.45v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 32. float waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. 0.45 v dd -0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh -0.1v v ol +0.1v v load +0.1v v load -0.1v timing reference points
44 at8xc51snd1c 4106f?8051?10/02 ordering information notes: 1. refers to rom code. 2. plcc84 package only available for development board. table 58. ordering information part number memory size supply voltage temperature range max frequency package (2) packing AT89C51SND1C-ROTIL 64k flash 3v industrial 40 mhz tqfp80 tray at83snd1axxx (1) -rotil 64k rom 3v industrial 40 mhz tqfp80 tray
45 at8xc51snd1c 4106f?8051?10/02 package information tqfp80
46 at8xc51snd1c 4106f?8051?10/02 plcc84
printedonrecycledpaper. atmel ? and dataflash ? are registered trademark of atmel. multimedia card ? is a registered trademark of multimedia coroporation. smartmedia ? is a registered trademark of toshiba corporation. compactflash ? is a trademark of compactflash corporation. other terms and product names may be the trademarks of others. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf data- com avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4106f?8051?10/02 /0m

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